ESRF to boost European nanoelectronics

Today’s microprocessors pack billions of transistors into a piece of silicon roughly the size of a postage stamp. This remarkable feat is possible thanks to complementary metal–oxide–semiconductor (CMOS) and silicon-on-insulator (SOI) techniques. But chip manufacturers need to push advanced lithography down to the atomic scale if they are to continue the relentless miniaturisation of transistors, which demands new technologies.

In April 2012, the French National Research Agency and the CEA established an eight-year long ¤460 m public–private programme called Institut de Recherche Technologique (IRT) “Nanoelec” to develop 3D assembly for increasingly complex chips, and silicon nanophotonics for faster communication within and between chips. IRT Nanoelec is one of seven major programmes established in France to leverage high-tech industry through public and private sector research. The ESRF together with the Institut Laue-Langevin (ILL) and the CEA are to share ¤6.5 m to help industry meet these goals.

The aim is to make it as simple as possible for companies to access beam time at large facilities. Based on experiments carried out by industrial partners and the ESRF, the programme will define preparation and characterisation processes for specific materials and devices. “The ESRF allows characterisation of microelectronic devices but it’s still difficult for enterprises to access the ESRF,” says Michel Wolny of the CEA and Director of IRT Nanoelec. “IRT will help the ESRF to open its capabilities to industry thanks to specific investments and networking among the 17 IRT partners.”

Industry on board

IRT Nanoelec partner Soitec uses X-ray diffraction and reflectivity techniques to characterise materials, but until now this has mostly been carried out using conventional diffractometers, explains IRT project co-ordinator for Soitec, Yves-Matthieu Le Vaillant. “The use of the synchrotron allows intense radiation and focused beams, resulting in a better accuracy at the sub-micron lateral scale,” he told ESRFnews. “It will allow unique observations of amorphous silicon dioxide layers and possibly III-V semiconductors for the solar industry.”

For 3D integration of chips, explains laboratory manager Nadine Bicaïs of STMicroelectronics, the ESRF provides a unique tool to characterise large-area silicon wafers. “Thanks to the high brilliance provided by the ESRF, X-ray based techniques allow us to observe large embedded features while maintaining state-of-the-art resolution.”

“This is an important project for us,” says Ed Mitchell of the ESRF’s Business Development Office. “Once we gain experience and expertise in working with these firms we can apply it to companies across Europe, thus extending the benefits to all ESRF funding states.”

Matthew Chalmers

This article first appeared in the July 2013 edition of ESRFNews.

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Top image: France's Nanoelec programme will leverage high-tech industry through public and private sector research.